Transistor High-K Layers

To improve transistor performance, one technique beyond traditional lithography scaling is to increase transistor capacitance by reducing the electrical thickness of the gate dielectric. Over the previous device generations, the semiconductor industry has moved from depositing ultra-thin silicon dioxide to medium-k nitrided silicon dioxide, and is now developing techniques to deposit high-k hafnium oxide-based dielectrics.

Jordan Valley XRR mode meets the process integration challenges of these new high-k materials by enabling characterization of the thickness and density of the hafnium oxide layers. In addition, operating in XRR mode can help refine the process used for deposition by detecting the detrimental presence of roughness and interfacial layers.

The XRD operating mode further enables high-k gate process integration by allowing the characterization of the onset of crystallization during implant anneal.

DRAM High-K Laminates

While circuit speed drives device performance improvements for logic, DRAM device performance depends on increasing the device density (Megabit per chip) by reducing the cell surface area. In the familiar 1T1C (1 transistor and 1 capacitor) design, the reduction of the cell surface area can be achieved by manufacturing smaller capacitor structures. A key enabling technology to reduce the capacitor size is the ability to use a high k dielectric between the capacitor plates. Metallic oxides are materials with very high k values; unfortunately these materials conduct electricity when exposed to a high enough potential. A practical technical solution to this problem is to engineer a compound material where the high k material is layered with a high band gap (Eg) compound, thus producing a composite with both high k and high Eg properties. This layering of materials gives rise to a superlattice to which XRR is particularly sensitive.

The Jordan Valley XRR mode, coupled with a super-lattice analysis algorithm, gives full characterization of the ALD deposition of high k nanolaminates, as well as characterization of its thermal budget. Measurements include thickness, density and atomic roughness. This makes Jordan Valley metrology solutions an essential tool in the development of advanced DRAM devices.

Metal Gate Layers

Metal gate stack is a technique to improve transistor performance on the ITRS roadmap for the 45nm manufacturing process. Metal gates offer the advantage of solving the polysilicon depletion problem as well as increasing gate capacitance when used in conjunction with a high-k gate dielectric. Adjusting the work function for PMOS and NMOS over bulk silicon or SOI requires the careful combination of two to three metal layers in the gate stack, each requiring thorough process control.

In XRR mode, Jordan Valley meets the process integration challenges of these metal stacks by providing definitive thickness and density measurement of individual layers. The system also analyzes crystallinity, phase and roughness properties.

For optimum throughput, the XRR/XRF dedicated configuration provides optimum throughput for uniformity inline sampling capability.

In XRD mode, Jordan Valley technology further enhances metal gate stack process integration capability by allowing the characterization of the gate microstructures after both deposition and anneal.